This invention is in the field of non-volatile memory integrated circuits. Embodiments of this invention are more specifically directed to the setting of an operational parameter in ferroelectric memory devices.
Conventional metal-oxide-semiconductor (MOS) and complementary MOS (CMOS) logic and memory devices are prevalent in modern electronic systems, as they provide an excellent combination of fast switching times and low power dissipation, along with their high density and suitability for large-scale integration. As is fundamental in the art, however, those devices are essentially volatile, in that logic and memory circuits constructed according to these technologies do not retain their data states upon removal of bias power. Especially in mobile and miniature systems, the ability to store memory and logic states in a non-volatile fashion is very desirable. As a result, various technologies for constructing non-volatile devices have been developed in recent years.
One non-volatile solid-state memory technology involves the construction of capacitors in which the dielectric material is a polarizable ferroelectric material, such as lead zirconate titanate (PZT) or strontium-bismuth-tantalate (SBT). Hysteresis in the charge-vs.-voltage (Q-V) characteristic of these ferroelectric capacitors enables the non-volatile storage of binary states after voltage has been removed from the capacitor plates, with the stored state corresponding to the polarization state of the ferroelectric material. In contrast, conventional MOS capacitors lose their stored charge upon removal of the capacitor voltage. It has been observed that ferroelectric capacitors can be constructed by processes that are largely compatible with modern CMOS integrated circuits, for example by placing capacitors above the transistor level and below the metal conductor levels.
FIG. 1 illustrates an example of a Q-V characteristic of a conventional ferroelectric capacitor. As shown, the charge (Q) stored across the conductive plates depends on the voltage applied to the plates (V), and also on the recent history of that voltage. If the voltage V applied across the capacitor plates exceeds a “coercive” voltage +Vα, the capacitor polarizes into the “+1” state. According to this characteristic, once polarized to the “+1” state, so long as voltage V remains above coercive voltage −Vβ, the capacitor exhibits a stored charge of +Q1. Conversely, if the voltage V applied across the capacitor plates is more negative than coercive voltage −Vβ, the capacitor is polarized into the “−1” state, and will exhibit a stored charge of −Q2 for applied voltage V below +Vα.
An important characteristic of ferroelectric capacitors, as used in non-volatile solid-state memory, is the difference in capacitance exhibited by a ferroelectric capacitor between its polarized states. As fundamental in the art, the capacitance of an element refers to the ratio of stored charge to applied voltage. While the ferroelectric capacitor has a linear capacitance by virtue of its construction as parallel plates separated by a dielectric film (i.e., the ferroelectric material), it also exhibits significant polarization capacitance (i.e., charge storage) in response to changes in polarization state that occurs upon application of a polarizing voltage. For example, referring to FIG. 1, the polarization of a ferroelectric capacitor from its “−1” state to its “+1” state is reflected in a relatively high capacitance C(−1), reflecting the storage of polarization charge in the capacitor in response to the change of polarization state by the voltage exceeding coercive voltage Vα. On the other hand, a capacitor that already in its “+1” state exhibits little capacitance C(+1) due to polarization, since its ferroelectric domains are already aligned in the direction of the applied coercive voltage, causing little additional polarization charge to be stored.
This ferroelectric behavior is being put to use in non-volatile ferroelectric read/write random access memory (RAM) devices, commonly referred to as “ferroelectric RAM”, or “FeRAM”, or “FRAM” devices. FRAMs are now commonplace in many electronic systems, particularly portable electronic devices and systems, and are especially attractive in implantable medical devices such as pacemakers and defibrillators. Various memory cell architectures including ferroelectric capacitors are known in the art, including the well-known 2T-2C (two transistor, two capacitor) cells in which the two ferroelectric capacitors in a cell are polarized to complementary states, with the polarity of that complementary polarization indicating the stored data state. As known in the art, the complementary polarized states of the 2T-2C cell present a differential signal to a pair of bit lines, in a read operation. This differential signal at the bit line pair is sensed by a differential sense amplifier in conventional memory architectures, to retrieve the stored data state.
Another known arrangement of a ferroelectric memory cell is the 1T-1C (one transistor, one capacitor) arrangement. The 1T-1C cell is attractive because of the small chip area required for this cell as compared with 2T-2C and larger (e.g., 6T) FRAM cell types. However, as will be described in further detail below, the sensing of 1T-1C FRAM cells is necessarily single-ended, and thus provides significantly less read margin than does the differential sensing of 2T-2C cells.
FIG. 2a illustrates a typical arrangement of a conventional 1T-1C FRAM cell 2jk, which represents a single cell residing in a row j and a column k of an array of similar cells 2. Cell 2jk includes n-channel pass transistor 4 and ferroelectric capacitor 6. The source/drain path of transistor 4 is connected between bit line BLk for column k of the array, and the top plate of ferroelectric capacitor 6; the gate of transistor 4 is controlled by word line WLj for row j of the array. The bottom plate of ferroelectric capacitor 6 is connected to plate line PL, which may be in common for all cells 2 in the array (or in a particular portion of the array, depending on the architecture). As such, 1T-1C FRAM cells are constructed similarly as conventional dynamic RAM memory cells. Sense amplifier 8 is coupled to bit line BLk, and operates to compare the bit line voltage developed by read current iR to a reference voltage VREF generated by reference voltage generator circuit 9, as will be described below.
As typical in the art for 1T-1C memory cells such as cell 2jk of FIG. 2a, the polarization state that exhibits the higher capacitance when sensed, which in this case is the “−1” polarization state, will be considered as the “1” data state, and the lower capacitance “+1” polarization state will be considered as the “0” data state. Cell 2jk is written by applying voltages to plate line PL and bit line BLk that, with word line WLj energized, polarizes capacitor 6 into the desired polarization state. In this example, a “0” data state corresponding to the “+1” polarization state of FIG. 1 is written by the application of a low voltage (Vss) to bit line BLk, turning on word line WLj, and then raising plate line PL to a high voltage (Vcc). Conversely, a “1” data state corresponding to the “−1” polarization state is written by the application of a low voltage (Vss) to plate line PL, turning on word line WLj, and then raising bit line BLk to a high voltage (Vcc).
The read operation of cell 2jk begins with the precharging of bit line BLk to a low voltage (e.g., Vss). As shown in FIG. 2b, once bit line BLk is precharged, word line WLj is energized to turn on transistor 4 and couple capacitor 6 to bit line BLk. The voltage of plate line PL from the low voltage Vss is then raised to the high voltage Vcc to interrogate the polarization capacitance of capacitor 6, according to the hysteresis diagram of FIG. 1. Specifically, the energizing of plate line PL induces a read current iR onto bit line BLk to develop a voltage on bit line BLk. As known in the art, the voltage level developed on bit line BLk depends on the capacitance exhibited by ferroelectric capacitor 6 in cell 2jk relative to the bit line capacitance. As shown in FIG. 2b, if capacitor 6 is in the “+1” polarization state, read current iR will be relatively low and will thus develop a relatively low level bit line voltage V(0). Conversely, the “−1” polarization state of capacitor 6 will result in a relatively strong read current iR, and higher level voltage V(1) at bit line BLk.
According to an “after-pulse sensing” approach as shown in FIG. 2b, sense amplifier 8 is activated at time tSA_ap, after the plate line PL pulse, at which time sense amplifier 8 compares the bit line voltage with the reference voltage VREF from reference voltage generator 9. To discern the stored data state, reference voltage VREF is set at a nominal voltage between the expected low and high data state levels V(0), V(1), respectively (i.e., within the window ΔV of FIG. 2b). Following time tSA_ap, sense amplifier 8 drives bit line BLk to a full logic “1” level in response to detecting the higher bit line voltage V(1), and to a full logic “0” level in response to detecting the lower bit line voltage V(0), as shown in FIG. 2b. 
Another conventional sense approach, referred to as “step sensing” or “on-pulse sensing” activates sense amplifier 8 during the plate line pulse, such as at time tSA_op shown in FIG. 2b. As known in the art and as shown in FIG. 2b, the bit line voltages V(0), V(1) exhibit a lower common mode voltage in the after-pulse sensing case, because the non-switching capacitance of the data “0” state does not contribute to the sensed voltage. After-pulse sensing is preferred in many implementations, to minimize the effect of variations in the non-switching capacitance of the ferroelectric capacitor on the bit line voltage.
In either case, the read of the “1” data state is destructive, because the read operation essentially programs cell 2jk into the opposite data state; a write-back operation (not shown in FIG. 2b) is then typically performed to return cell 2jk to its previous polarization state.
As evident from the foregoing description, the read signal from 1T-1C FRAM cell 2jk is single-ended, and is sensed by comparison with a reference level such as reference voltage VREF. In contrast, 2T-2C FRAM cells provide a differential signal to the sense amplifier, where the data state is indicated by the polarity of the complementary bit line voltages from the cell. As such, and as mentioned above, read margin is a significant issue with 1T-1C FRAM cells.
FIG. 3 illustrates an example of cumulative bit fail distributions with reference voltage for a conventional 1T-1C FRAM memory, for both data states. Curves 100 and 101 respectively indicate the numbers of “0” data state bits and “1” data state bits that fail at various reference voltages VREF (expressed in reference units relative to the reference voltage at which the strongest “0” cell fails). As evident to those skilled in the art from FIG. 3, lower reference voltages VREF will be more difficult for “0” data states and easier for “1” data states to be correctly read, and higher reference voltages VREF will be more difficult for “1” data states and easier for “0” data states to be correctly read. Stated another way, movement of reference voltage VREF in one direction will improve the read margin for one data state, but will reduce the read margin for the other data state. Accordingly, conventional FRAM memories typically set the level of their reference voltage VREF for normal operation at a voltage that is equidistant from the level at which the weakest “0” cell fails and the level at which the weakest “1” cell fails, in order to maximize the worst case read margin. As shown in FIG. 3, reference voltage VREF is set at a level that is Δ/2 above the “0's limit” at which the weakest “0” cell fails and Δ/2 above the “1's limit” at which the weakest “1” cell fails, where 4 is the difference between the 0's limit and the 1's limit. In practice, this mid-point reference voltage level is typically set during electrical test of each device, for example by programming a configuration register or the like based on test results of the cells in each device at varying reference voltages.
By way of further background, copending and commonly assigned U.S. Patent Application Publication US 2015/0357050, incorporated herein by reference, describes a data retention reliability screen of FRAM cells in which a reference voltage level for the read of a high polarization capacitance data state (e.g., a “1” state) is determined for each integrated circuit being tested. A number of FRAM cells in the integrated circuit are programmed to the “1” data state, and then read at an elevated temperature. The number of failing cells is compared against a pass/fail threshold to determine whether that integrated circuit is vulnerable to long-term data retention failure.
By way of further background, copending and commonly assigned U.S. application Ser. No. 14/857,873, filed Sep. 18, 2015 and incorporated herein by reference, describes a data retention reliability screen of FRAM memory arrays in which sampled groups of cells are tested at varying reference voltage levels, after programming to the high polarization capacitance state and after a relaxation pause at an elevated temperature. A test reference voltage is derived from fail bit counts of the sample groups for use in testing all of the FRAM cells in the integrated circuit.